library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity tb_Mem_ram_vs2 is end entity tb_Mem_ram_vs2; architecture testes of tb_Mem_ram_vs2 is -- Sinais para interfaceamento com a UUT: signal clock, resetn, cen : std_logic; signal dado : std_logic_vector (7 downto 0); signal wren, rden : std_logic; signal saida : std_logic_vector (7 downto 0); begin UUT: entity work.Mem_ram_vs2 port map ( clock, resetn, cen, wren, rden, dado, saida ); Gera_Clock: process begin -- simulação do pressionamento do botão de reset. resetn <= '0' after 0 ms, '1' after 1 ms, '0' after 50 ms; clock <= '0'; wait for 1 ms; -- rotina de geração de clock while resetn = '1' loop clock <= not clock; wait for 20833 ps; end loop; wait; end process; Envia_dados: process begin cen <= '0'; wren <='1'; rden <='1'; dado <= x"01"; wait for 1 ms; wren <= '0'; wait for 500 us; wren <= '1'; wait for 500us; dado <= x"02"; wait for 1 ms; wren <= '0'; wait for 1 ms; wren <= '1'; wait for 5 ms; rden <= '0'; wait for 1 ms; wren <='1'; rden <='1'; dado <= x"03"; wait for 1 ms; wren <= '0'; wait for 500 us; wren <= '1'; wait for 500us; dado <= x"04"; wait for 1 ms; wren <= '0'; wait for 500 us; wren <= '1'; wait for 1 ms; wren <='1'; rden <='1'; dado <= x"05"; wait for 1 ms; wren <= '0'; wait for 500 us; wren <= '1'; wait for 500 us; dado <= x"06"; wait for 1 ms; wren <= '0'; wait for 500 us; wren <= '1'; wait for 500us; dado <= x"07"; wait for 1 ms; wren <= '0'; wait for 500 us; wren <= '1'; wait for 500us; dado <= x"08"; wait for 1 ms; wren <= '0'; wait for 500 us; wren <= '1'; wait for 1 ms; rden <= '0'; wait for 1 ms; rden <= '1'; wait for 1 ms; rden <= '0'; wait for 1 ms; rden <= '1'; wait for 1 ms; rden <= '0'; wait for 1 ms; rden <= '1'; wait for 1 ms; rden <= '0'; wait for 1 ms; rden <= '1'; wait for 1 ms; rden <= '0'; wait for 1 ms; rden <= '1'; wait for 1 ms; rden <= '0'; wait for 1 ms; rden <= '1'; wait for 1 ms; rden <= '0'; wait for 1 ms; rden <= '1'; wait for 1 ms; rden <= '0'; wait for 1 ms; rden <= '1'; wait; end process; end architecture testes;